1. Field of the Invention
The present invention relates to a semiconductor device of a channelless gate array type having CMOS and biopolar transistors regularly formed on a common chip.
2. Description of the Related Art
FIG. 1 shows a standard cell array as a BiCMOS gate array as disclosed in Japanese Patent Disclosure (KOKAI) No. 60-16575 and FIG. 2 shows a detailed arrangement of a standard cell of the BiCMOS gate array of the Japanese KOKAI as set forth above.
In FIGS. 1 and 2, reference numeral 10 shows a gate array chip; 11, a standard cell; 12, standard cell rows; 13, a wiring layer; 14, an input/output circuit formation area and bonding pad formation area; 21, 22, bipolar transistors; 23, a PMOS transistor; 24, an NMOS transistor; and 25, 26, resistors The BiCMOS gate arrangement shown in FIG. 2 contains two PMOS transistors, two NMOS transistors 24 as well as two bipolar transistors and two resistors relative to these P and N transistors. A whole layout of the gate array chip 10 comprises a standard cell array and wiring layers 13 each formed between the cell rows. The resistors 25 and 26 as shown in FIG. 2 are of a diffusion type having a fixed resistive value
In the conventional array pattern system as shown in FIG. 2, two bipolar transistors are contained in the standard cell 11, increasing the chip size and extending a wiring layer length for gate-to-gate connection. As a result, a load capacity involved is increased, failing to obtain a high-speed feature which is one object of the BiCMOS gate. At the area of a samller load capacity, such as a shorter gate-to-gate wiring layer length area at a wiring pattern in the chip or an area where less number of gates are connected, the CMOS gate operates at a higher speed than the BiCMOS gate. It is at a relatively great load capacity area that a high-speed operation is achieved by the BiCMOS gate. It is, therefore, unnecessary to employ BiCMOS gates for all of the logic gates involved; that is, it is thus possible to employ CMOS gates in place of some BiCMOS gates. In spite of this situation, an excess number of bipolar transistors as used in the conventional array pattern system.
If, in the formation of a two-input BiCMOS NAND gate on a gate array chip as shown in FIG. 3 and a four input BiCMOS NOR gate on a gate array chip as shown in FIG. 4, the resistive value of the resistor 25 or 26 is made constant irrespective of the types of the logic gates, either one of the logic gates decreases in operation speed and increases in dissipation power. In FIGS. 3 and 4, reference numeral, 42 to 45 show input terminals; 46, an output terminal; 40, a power supply terminal (a positive voltage in this case) and 41, a ground terminal, noting that the circuit as shown in these Figures is of a pseudo ECL logic gate type. In FIG. 4, the four transistors 23 are connected in series with each other in which case the series resistance becomes greater than as shown in FIG. 3. Given that the resistive value of the resistor 25 is set equal in the circuit as shown in FIGS. 3 and 4, the base current of the transistor 21 becomes smaller in the circuit of FIG. 4 than in the circuit of FIG. 3 and the operation speed of the transistor 21 is delayed in the circuit of FIG. 4 upon comparison with that in the circuit of FIG. 3. In order to increase the operation speed in the circuit of FIG. 4, it will be necessary to make the resistive value of the resistor 25 greater than that in the circuit shown in FIG. 3. Furthermore, if the resistive values of the resistors 25 and 26 are not proper, the dissipation current of the respective logic gate cannot be held at a proper level.